Functions related to memory.
- See also
- Masked Memory
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| Load |
| Functions for loading Vec's from memory.
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| Store |
| Functions for storing Vec's to memory.
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static void | simd::lfence () |
| Load fence.
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template<size_t SIMD_WIDTH, typename T > |
static void | simd::load_store (const T *const src, T *const dst) |
| Copies a single Vec from one aligned memory location to another aligned memory location.
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template<size_t SIMD_WIDTH, typename T > |
static void | simd::load_storeu (const T *const src, T *const dst) |
| Copies a single Vec from one aligned memory location to another unaligned memory location.
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template<size_t SIMD_WIDTH, typename T > |
static void | simd::loadu_store (const T *const src, T *const dst) |
| Copies a single Vec from one unaligned memory location to another aligned memory location.
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template<size_t SIMD_WIDTH, typename T > |
static void | simd::loadu_storeu (const T *const src, T *const dst) |
| Copies a single Vec from one unaligned memory location to another unaligned memory location.
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static void | simd::mfence () |
| Full memory fence.
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static void | simd::sfence () |
| Store fence.
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◆ lfence()
static void simd::lfence |
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inlinestatic |
Load fence.
Forces strong memory ordering (serialization) between load instructions preceding this instruction and load instructions following this instruction, ensuring the system completes all previous loads before executing subsequent loads.
- Note
- May be implemented as a full memory barrier on some architectures.
◆ load_store()
template<size_t SIMD_WIDTH, typename T >
static void simd::load_store |
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const T *const | src, |
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T *const | dst ) |
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inlinestatic |
Copies a single Vec from one aligned memory location to another aligned memory location.
Both memory locations must be aligned to the SIMD_WIDTH.
- Parameters
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[in] | src | pointer to the aligned source memory location |
[out] | dst | pointer to the aligned destination memory location |
◆ load_storeu()
template<size_t SIMD_WIDTH, typename T >
static void simd::load_storeu |
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const T *const | src, |
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T *const | dst ) |
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inlinestatic |
Copies a single Vec from one aligned memory location to another unaligned memory location.
The source memory location must be aligned to the SIMD_WIDTH, the destination memory location does not have to be aligned to any boundary.
- Parameters
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[in] | src | pointer to the aligned source memory location |
[out] | dst | pointer to the unaligned destination memory location |
◆ loadu_store()
template<size_t SIMD_WIDTH, typename T >
static void simd::loadu_store |
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const T *const | src, |
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T *const | dst ) |
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inlinestatic |
Copies a single Vec from one unaligned memory location to another aligned memory location.
The destination memory location must be aligned to the SIMD_WIDTH, the source memory location does not have to be aligned to any boundary.
- Parameters
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[in] | src | pointer to the unaligned source memory location |
[out] | dst | pointer to the aligned destination memory location |
◆ loadu_storeu()
template<size_t SIMD_WIDTH, typename T >
static void simd::loadu_storeu |
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const T *const | src, |
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T *const | dst ) |
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inlinestatic |
Copies a single Vec from one unaligned memory location to another unaligned memory location.
Both memory locations do not have to be aligned to any boundary.
- Parameters
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[in] | src | pointer to the unaligned source memory location |
[out] | dst | pointer to the unaligned destination memory location |
◆ mfence()
static void simd::mfence |
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inlinestatic |
Full memory fence.
Forces strong memory ordering (serialization) between load and store instructions preceding this instruction and load and store instructions following this instruction, ensuring that the system completes all previous memory accesses before executing subsequent memory accesses.
◆ sfence()
static void simd::sfence |
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inlinestatic |
Store fence.
Forces strong memory ordering (serialization) between store instructions preceding this instruction and store instructions following this instruction, ensuring the system completes all previous stores before executing subsequent stores.
- Note
- May be implemented as a full memory barrier on some architectures.