T-SIMD v31.1.0
A C++ template SIMD library
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Memory

Description

Functions related to memory.

See also
Masked Memory

Subgroups

 Load
 Functions for loading Vec's from memory.
 
 Store
 Functions for storing Vec's to memory.
 

Functions

static void simd::lfence ()
 Load fence.
 
template<size_t SIMD_WIDTH, typename T >
static void simd::load_store (const T *const src, T *const dst)
 Copies a single Vec from one aligned memory location to another aligned memory location.
 
template<size_t SIMD_WIDTH, typename T >
static void simd::load_storeu (const T *const src, T *const dst)
 Copies a single Vec from one aligned memory location to another unaligned memory location.
 
template<size_t SIMD_WIDTH, typename T >
static void simd::loadu_store (const T *const src, T *const dst)
 Copies a single Vec from one unaligned memory location to another aligned memory location.
 
template<size_t SIMD_WIDTH, typename T >
static void simd::loadu_storeu (const T *const src, T *const dst)
 Copies a single Vec from one unaligned memory location to another unaligned memory location.
 
static void simd::mfence ()
 Full memory fence.
 
static void simd::sfence ()
 Store fence.
 

Function Documentation

◆ lfence()

static void simd::lfence ( )
inlinestatic

Load fence.

Forces strong memory ordering (serialization) between load instructions preceding this instruction and load instructions following this instruction, ensuring the system completes all previous loads before executing subsequent loads.

Note
May be implemented as a full memory barrier on some architectures.

◆ load_store()

template<size_t SIMD_WIDTH, typename T >
static void simd::load_store ( const T *const src,
T *const dst )
inlinestatic

Copies a single Vec from one aligned memory location to another aligned memory location.

Both memory locations must be aligned to the SIMD_WIDTH.

Parameters
[in]srcpointer to the aligned source memory location
[out]dstpointer to the aligned destination memory location

◆ load_storeu()

template<size_t SIMD_WIDTH, typename T >
static void simd::load_storeu ( const T *const src,
T *const dst )
inlinestatic

Copies a single Vec from one aligned memory location to another unaligned memory location.

The source memory location must be aligned to the SIMD_WIDTH, the destination memory location does not have to be aligned to any boundary.

Parameters
[in]srcpointer to the aligned source memory location
[out]dstpointer to the unaligned destination memory location

◆ loadu_store()

template<size_t SIMD_WIDTH, typename T >
static void simd::loadu_store ( const T *const src,
T *const dst )
inlinestatic

Copies a single Vec from one unaligned memory location to another aligned memory location.

The destination memory location must be aligned to the SIMD_WIDTH, the source memory location does not have to be aligned to any boundary.

Parameters
[in]srcpointer to the unaligned source memory location
[out]dstpointer to the aligned destination memory location

◆ loadu_storeu()

template<size_t SIMD_WIDTH, typename T >
static void simd::loadu_storeu ( const T *const src,
T *const dst )
inlinestatic

Copies a single Vec from one unaligned memory location to another unaligned memory location.

Both memory locations do not have to be aligned to any boundary.

Parameters
[in]srcpointer to the unaligned source memory location
[out]dstpointer to the unaligned destination memory location

◆ mfence()

static void simd::mfence ( )
inlinestatic

Full memory fence.

Forces strong memory ordering (serialization) between load and store instructions preceding this instruction and load and store instructions following this instruction, ensuring that the system completes all previous memory accesses before executing subsequent memory accesses.

◆ sfence()

static void simd::sfence ( )
inlinestatic

Store fence.

Forces strong memory ordering (serialization) between store instructions preceding this instruction and store instructions following this instruction, ensuring the system completes all previous stores before executing subsequent stores.

Note
May be implemented as a full memory barrier on some architectures.